In recent years, there is a demand for improvement in a device operation speed and increase in memory capacity for achieving high integration and high performance of a semiconductor device. Recently, a COC (Chip on Chip) device, in which a logic chip and a large-capacity DRAM are stacked, is also developed instead of an eDRAM (Embedded Dynamic Random Access Memory) chip.
In the COC device, in one chip, two types of terminals, i.e., a terminal (hereinafter, first terminal) for connection to the other chip and a terminal (hereinafter, second terminal) for connection to the outside are required in some cases. Moreover, the first terminal and the second terminal are required to be formed into different shapes appropriate for each of them. Specifically, the first terminal is required to form a bump to have sufficient height. The second terminal is required to use an electrode pad formed in a chip. In forming such two types of terminals, the terminals are formed by using, for example, a redistribution technology, for example, in Japanese Patent Application Laid-open No. 2008-84962.
In Japanese Patent Application Laid-open No. 2008-84962, a tip side of a redistribution is patterned into a pad shape to be a connection terminal portion. Then, especially, this connection terminal portion is plated on its surface with nickel (Ni) and gold (Au), so that an electrical contactability and a bondability in wire bonding can be improved. In other words, Japanese Patent Application Laid-open No. 2008-84962 discloses that a laminated structure of nickel (Ni) and gold (Au) is applied only to the surface layer of the second terminal. However, Japanese Patent Application Laid-open No. 2008-84962 does not disclose a specific process of forming this structure selectively on the second terminal.